1. Field of the Invention
The present invention relates to a sensing circuit for a magnetic memory unit, and more particularly, to a sensing circuit able to rapidly read bit information stored in the magnetic memory unit.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a circuit diagram of a magnetic memory unit 10 of the prior art. The magnetic memory unit 10 comprises a sensing circuit 20, a first switch 32, a current source 36 with a fixed value, at least one magnetic resistor 38, 138, 238, and 338, and at least one read line 39, 139, 239, and 339. The magnetic memory unit 10 corresponds to an address decoder 42 connected with the first switch 32 and the first switch is turned on if the magnetic memory unit 10 is chosen by the address decoder 42. The address decoder is also connected to the read line 39, 139, 239, and 339 for determining which switch is turned on or not. The current source 36 provides a bias current.
The sensing circuit comprises an inverter 22, a capacitor 28 and a second switch 34. The inverter 22 has an input 24 and an output 26. The capacitor 28 is connected electrically to the input 24 of the inverter 22, and to the current source 36. The second switch 34 is connected electrically to the input 24 and the output 26 of the inverter 22.
When the read line 39 is turned on, a magnetic field induced by a current passing through the read line 39 interacts with the magnetic resistor 38 having different resistance values, due to the two magnetized directions of the resistor.
A first voltage sum of the voltages while the current source 36 passes through the magnetic resistors 38, 138, 238, and 338, is outputted to the capacitor 28 if one of the read lines 39, 139, 239, 339 is turned on. At the same time, the second switch 34 is turned on setting the input 24 and the output 26 of the inverter 22 equal to a second voltage. This technique is referred to as zeroing. A voltage across the capacitor 28 is the difference between the first voltage and the second voltage.
When the second switch 34 is turned off there is a difference in the voltages outputted to the capacitor 28 caused also by the magnetized directions of the magnetic resistors being in different directions. Following this, the voltages of the input 24 of the inverter 22 vary with different voltages outputted to the capacitor 28, and the output end 26 of the inverter 22 responds to variations of different voltages to the input 24, and shows complementary outputs in comparison with the voltages of the input 24. By sensing the voltages of the output 26, it is not very difficult to achieve bit information storage for the magnetic memory unit 10.
Finally, the second switch is turned on for equalizing the voltages of the input 24 and the output 26 and in preparation for reading the next bit of information.
Please refer to FIG. 2. FIG. 2 is an input and output relationship diagram of the sensing circuit 20 of the magnetic memory unit 10. V24 and V26 represent the voltages of the input 24 and the output 26 of the inverter 22, respectively. When the second switch 34 of FIG. 1 is turned on, the value of voltage V24 and voltage V26 are equal. After sensing voltages of the output 26 of the inverter 22, the sensing circuit 20 of FIG. 1 undergoes zeroing to make sure the bit information sensed next time is accurate. But when the second switch 34 is turned on, a small amount of charge from the second switch 34 moves to the input end 24, resulting in a large variation of V26 so that the voltage sensed by the sensing circuit 20 is not the true value of V26.
It is therefore an objective of the present invention to provide a sensing circuit that has not only a high sensitivity, but also allows bit information stored in a magnetic memory unit to be sensed rapidly and accurately, using positive feedback for regenerating the bit information.
In accordance with the claimed invention, a magnetic memory unit includes at least one magnetic resistor and a sensing circuit with a first inverter and a second inverter electrically connected in a back-to-back fashion forming a latch, an enabler for enabling the first inverter and the second inverter, a first capacitor, a second capacitor, and an equalizer.
It is an advantage of the present invention that the present invention provides a sensing circuit with a symmetric structure, with this kind of sensing circuit able to achieve the same amount of charge injection occurring in an input end and an output end of the sensing circuit. This leads to a more accurate and rapid result.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in various figures and drawings.